1. Technical Field
The present disclosure relates to a variable shifter, a decoder, and a data shifting method.
2. Description of the Related Art
Low-density parity-check (LDPC) codes have been known for error-correction encoding methods that can realize bit error rates close to the Shannon limit and that can realize decoders in large scale integration (LSI).
In recent years, among LDPC codes, Quasi-Cyclic LDPC (QC-LDPC) codes with which it is relatively easy to configure encoders have been known. QC-LDPC has been utilized in many industrial fields. QC-LDPC codes are used, for example, in IEEE standard 802.11n used for wireless local area networks (LANs) and in IEEE standard 802.11ad, which is a short-distance wireless communication standard using the 60 GHz band.
Details of the IEEE 802.11ad standard are disclosed in IEEE 802.11ad-2012, 21.3.8, Page 452 (Non-Patent Document 1).
Data encoded with a QC-LDPC code is decoded by an LDPC decoder. For example, a sum-product decoding method, a min-sum decoding method, and a bit-flipping decoding method are known LDPC decoding methods using an LDPC decoder. In any of the decoding methods, barrel shifters shift data, and variable node processing and check node processing are repeated to perform decoding. For example, LDPC decoders applied to high-speed wireless communication perform each of the variable node processing and the check node processing in parallel.
The configuration of an LDPC decoder of the related art is described in Matthew Weiner; Borivoje Nikolic; Zhengya Zhang; “LDPC Decoder Architecture for High-Data Rate Personal-Area Networks” IEEE International Symposium on Circuits and Systems (ISCAS), 2011, Pages 1784-1787 (this document is hereinafter referred to as “Non-Patent Document 2”). Non-Patent Document 2 describes an offset min-sum decoding method, which is one type of min-sum decoding method.